`timescale 1ns / 1ns

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:56:18 11/13/2011
// Design Name:   serial_in
// Module Name:   /home/uraj/opt/Xilinx/13.1/test/test_input.v
// Project Name:  test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: serial_in
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_input;

	// Inputs
	reg [31:0] din;
	reg clk;
	reg rst;

	// Outputs
	wire [2047:0] dout;
	wire [5:0] oaddr;
	wire [1:0] iwen;
	wire busy;
    wire [31:0]   out_array[63:0];
    assign out_array[ 0] = dout[  31:   0];
    assign out_array[ 1] = dout[  63:  32];
    assign out_array[ 2] = dout[  95:  64];
    assign out_array[ 3] = dout[ 127:  96];
    assign out_array[ 4] = dout[ 159: 128];
    assign out_array[ 5] = dout[ 191: 160];
    assign out_array[ 6] = dout[ 223: 192];
    assign out_array[ 7] = dout[ 255: 224];
    assign out_array[ 8] = dout[ 287: 256];
    assign out_array[ 9] = dout[ 319: 288];
    assign out_array[10] = dout[ 351: 320];
    assign out_array[11] = dout[ 383: 352];
    assign out_array[12] = dout[ 415: 384];
    assign out_array[13] = dout[ 447: 416];
    assign out_array[14] = dout[ 479: 448];
    assign out_array[15] = dout[ 511: 480];
    assign out_array[16] = dout[ 543: 512];
    assign out_array[17] = dout[ 575: 544];
    assign out_array[18] = dout[ 607: 576];
    assign out_array[19] = dout[ 639: 608];
    assign out_array[20] = dout[ 671: 640];
    assign out_array[21] = dout[ 703: 672];
    assign out_array[22] = dout[ 735: 704];
    assign out_array[23] = dout[ 767: 736];
    assign out_array[24] = dout[ 799: 768];
    assign out_array[25] = dout[ 831: 800];
    assign out_array[26] = dout[ 863: 832];
    assign out_array[27] = dout[ 895: 864];
    assign out_array[28] = dout[ 927: 896];
    assign out_array[29] = dout[ 959: 928];
    assign out_array[30] = dout[ 991: 960];
    assign out_array[31] = dout[1023: 992];
    assign out_array[32] = dout[1055:1024];
    assign out_array[33] = dout[1087:1056];
    assign out_array[34] = dout[1119:1088];
    assign out_array[35] = dout[1151:1120];
    assign out_array[36] = dout[1183:1152];
    assign out_array[37] = dout[1215:1184];
    assign out_array[38] = dout[1247:1216];
    assign out_array[39] = dout[1279:1248];
    assign out_array[40] = dout[1311:1280];
    assign out_array[41] = dout[1343:1312];
    assign out_array[42] = dout[1375:1344];
    assign out_array[43] = dout[1407:1376];
    assign out_array[44] = dout[1439:1408];
    assign out_array[45] = dout[1471:1440];
    assign out_array[46] = dout[1503:1472];
    assign out_array[47] = dout[1535:1504];
    assign out_array[48] = dout[1567:1536];
    assign out_array[49] = dout[1599:1568];
    assign out_array[50] = dout[1631:1600];
    assign out_array[51] = dout[1663:1632];
    assign out_array[52] = dout[1695:1664];
    assign out_array[53] = dout[1727:1696];
    assign out_array[54] = dout[1759:1728];
    assign out_array[55] = dout[1791:1760];
    assign out_array[56] = dout[1823:1792];
    assign out_array[57] = dout[1855:1824];
    assign out_array[58] = dout[1887:1856];
    assign out_array[59] = dout[1919:1888];
    assign out_array[60] = dout[1951:1920];
    assign out_array[61] = dout[1983:1952];
    assign out_array[62] = dout[2015:1984];
    assign out_array[63] = dout[2047:2016];
	// Instantiate the Unit Under Test (UUT)
	serial_in uut (
		.din(din), 
		.clk(clk), 
		.rst(rst), 
		.dout(dout), 
		.oaddr(oaddr), 
		.iwen(iwen), 
		.busy(busy)
	);

	initial begin
		// Initialize Inputs
		din = 0;
		clk = 0;
		rst = 1;

		// Wait 100 ns for global reset to finish
		#100;
        rst = 0;

		// Add stimulus here

	end
    
    always begin
        #50;
        clk = ~clk;
    end
    always begin
        #100
        din = din + 1;
    end

endmodule

